One very important aspect of implementing an IP core, is to validate that it is working as expected. Or to figure out why that damn piece of code is not doing what the master told him to do. The first, and most of the times the second thing as well are done using test-benches in VHDL. A test-bench provides the input for the ip core in such a way that it reaches a state where something interesting is happening. For validation the outputs are then verified with asserts such that an error occurs during simulation when something unexpected is happening.
Some people argue that VHDL is well suited for simulation, and in fact that is one of its biggest strength that you can write the test-bench in the same language as the ip core itself. After all, that is true for Java with JUnits for example. The problem is, this holds only true as long your are programming esoterically small examples like ripple carry adders. But what about your new H.264 acceleration core? Are you really going to implement it in a structural way that is fit for synthesis and then again in behavioral? What are the chances that you are doing the same error twice?
A far more common case is that you use an implementation written in language X as your reference. So the new workflow looks then like this: You run your reference implementation with some input, write its output in a format that can be read by your VHDL test-bench, then run your test-bench and validate that the output matches. This workflow is so cumbersome to use that you will either spend a lot of time on getting the conversion steps automated, or you just don't test it very intensively.
While PSHDL allows you to define test-benches as well, it has another, much more powerful way of testing. PSHDL can generate a byte-code file for you. This PSEX, as I call it, is a very simple byte code that can easily be implemented in any language. Of course the reference implementation is available in Java, another one in C++ is currently under development. So what is the advantage of having byte-code?
Why byte code?
An interpreter for byte code is essentially just a big switch case. It takes about 1-2k lines of code to implement in most languages. This interpreter then can take the same input as your reference implementation and you can directly compare its outputs. No more intermediate files! But you can go even further with this. First of all, because PSHDL is also a framework, you can easily replace the byte code during runtime, which allows you to work with real-time data and work on them in a live way. Think about it, you can tweak your audio codec while it is processing some real data. The current interpreter will probably not be fast enough for this advanced processing, but it is not too hard to create a JIT compiler for it as well.
Seeing is believing, so here is a video of it showing it in action.
Get your blinking LEDs onto real hardware in seconds without having to learn any vendor tools! Zero installation required!
You might say that an interpreter running on the FPGA kind of in SW is much slower than a proper synthesis, that is absolutely correct. But for teaching ripple carry adders, and some simple IO stuff that is sufficient.