Just today I was wondering how much code I wrote for the PSHDL compiler. The numbers are pretty interesting. The core code of PSHDL is split like this:
I was curious on how much of that code I actually wrote on my own. And this is the result:
So it can easily be seen that a lot of my code is generated. The PSHDL AST code is generated from my DSL (Domain specific language) model. The ANTLR part is the code generated by the parser generator that I need for parsing input files. The XTend Output on the other hand is generated from the 4282 lines of input code. So to compare the input and generated output:
What can we learn from this?
A lot of code in the PSHDL compiler is generated from a sparse description. This has distinct advantages for maintenance. For example the code for the AST model contains lots of boilerplate code for things like hashing, equals, getter, modifier, constructors and other things. Writing this code is not just boring, writing it on your own is also very error prone. This is why PSHDL features generators that can generate this boilerplate code for you. One of our IPCores has 325 lines of PSHDL code. From this we generate the following code:
In a rough estimate the ratio of lines of PSHDL to lines of VHDL code is about 3 when the generator is not used. That means for 100 lines of PSHDL you get 300 lines of VHDL code. Another interesting thing to observe is the fact that very specialized generators can have crazy ratios from input to output, whereas the ratio gets down the more general a language gets. The ratio of 1:3 for PSHDL is possible because PSHDL is designed for (FPGA) Synthesis (and a little test-benching).
Another thing to consider is that the generated code can either be more compact or less compact than hand written output code. For XTend I found that the generated code is about twice as long as I would write it by hand. So you can say that 1 line of XTend is as powerful as 1 line of Java. But what is more important here is the readability. The XTend code is far more precise and easy to understand than the Java code. The generated VHDL code however is probably slightly smaller than what you would write by hand. This is caused by the fact that in for example a state machine typically 3 processes are used, while PSHDL will have just 2 in most cases.