In this blog I try to outline my motivation for the creation of PSHDL, which by the way stands for Plain Simple Hardware Description Language. As the name itself already suggests, a great emphasis had been put on creating a language that is easy to learn and fun to work with. Unlike VHDL which I hate with a passion. So expect many rumbling rants about VHDL here. If you're thinking: good, I am programming Verilog, well I think that Verilog has the same problems in most cases, so it is just slightly better than VHDL, but not enough to make a difference.
If you have any feedback about PSHDL, don't hesitate to contact me. It is far from being perfect, but every bug report I get, helps to improve it.